Search
Now showing items 1-10 of 18
Drift-Diffusion Versus Monte Carlo Simulated ON-Current Variability in Nanowire FETs
(IEEE, 2019)
Variability of semiconductor devices is seriously limiting their performance at nanoscale. The impact of variability can be accurately and effectively predicted by computer-aided simulations in order to aid future device ...
Spatial Sensitivity of Silicon GAA Nanowire FETs Under Line Edge Roughness Variations
(IEEE, 2018)
Standard analysis of variability sources in nanodevices lacks information about the spatial influence of the variability. However, this spatial information is paramount for the industry and academia to improve the design ...
Contribution to the Physical Modelling of Single Charged Defects Causing the Random Telegraph Noise in Junctionless FinFET
(MDPI, 2020)
In this paper, different physical models of single trap defects are considered, which are localized in the oxide layer or at the oxide–semiconductor interface of field effect transistors. The influence of these defects ...
FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
(IEEE, 2018)
Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate ...
Simulation of DIBL effect in 25 nm SOI-FinFET with the different body shapes
(ITMO University, 2017)
Short channel effects, such as DIBL are compared for SOI-FinFETs with different silicon body geometries. The original device considered was
straight without narrowing at the top and a set of devices that exhibit the ...
Study of basic vector operations on Intel Xeon Phi and NVIDIA Tesla using OpenCL
(Universidad de Granada, 2015)
The present work is an analysis of the performance of the basic vector operations AXPY,
DOT and SpMV using OpenCL. The code was tested on the NVIDIA Tesla S2050 GPU and
Intel Xeon Phi 3120A coprocessor. Due to the nature ...
A new AXT format for an efficient SpMV product using AVX-512 instructions and CUDA☆,☆☆,★
(Elsevier, 2021)
The Sparse Matrix-Vector (SpMV) product is a key operation used in many scientific applications. This work proposes a new sparse matrix storage scheme, the AXT format, that improves the SpMV performance on vector capability ...
Spin-polarized transport in a full magnetic pn tunnel junction
(AIP Publishing, 2011)
Simulations of the tunneling current as a function of voltage and temperature for a Zener diode
where both sides are ferromagnetic have been performed. The current is evaluated as a function
of the applied bias, the ...
A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs
(MDPI, 2019)
An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate ...
Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
(IEEE, 2020)
Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (L G ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte ...