Study of basic vector operations on Intel Xeon Phi and NVIDIA Tesla using OpenCL
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Título: | Study of basic vector operations on Intel Xeon Phi and NVIDIA Tesla using OpenCL |
Autor/a: | Coronado Barrientos, Edoardo Indalecio Fernández, Guillermo García Loureiro, Antonio Jesús |
Centro/Departamento: | Universidade de Santiago de Compostela. Centro de Investigación en Tecnoloxías da Información Universidade de Santiago de Compostela. Departamento de Electrónica e Computación |
Palabras chave: | Nvidia Tesla | Intel Xeon Phi | OpenCL | Kernel | Vector operations | AXPY | DOT | SPMV | |
Data: | 2015 |
Editor: | Universidad de Granada |
Cita bibliográfica: | Coronado Barrientos, E., Indalecio Fernández, G. and García Loureiro, A. (2015). Study of basic vector operations on Intel Xeon Phi and NVIDIA Tesla using OpenCL, v. 2, n. 1, pp. 26-40 |
Resumo: | The present work is an analysis of the performance of the basic vector operations AXPY, DOT and SpMV using OpenCL. The code was tested on the NVIDIA Tesla S2050 GPU and Intel Xeon Phi 3120A coprocessor. Due to the nature of the AXPY function, only two versions were implemented, the routine to be executed by the CPU and the kernel to be executed on the previously mentioned devices. It was studied how they perform for different vector’s sizes. Their results show the NVIDIA architecture better suited for the smaller vectors sizes and the Intel architecture for the larger vector’s sizes. For the DOT and SpMV functions, there are three versions implemented. The first is the CPU routine, the second one is an OpenCL kernel that uses local memory and the third one is an OpenCL kernel that only uses global memory. The kernels that use local memory are tested by varying the size of the work-group; the kernels that only uses global memory are tested by varying the arrays size. In the case of the first ones, the results show the optimum work-group size and that the NVIDIA architecture benefits from the use of local memory. For the latter kernels, the results show that larger computational loads benefits the Intel architecture |
Versión do editor: | http://revistaseug.ugr.es/index.php/amgp/article/view/3056 |
URI: | http://hdl.handle.net/10347/17698 |
ISSN: | 2341-3158 |
Dereitos: | This work is licensed under a Creative Commons Attribution 3.0 License |
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