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dc.contributor.authorNieto Lareo, Alejandro Manuel
dc.contributor.authorBrea Sánchez, Víctor Manuel
dc.contributor.authorLópez Vilariño, David
dc.contributor.authorOsorio, Roberto R.
dc.date.accessioned2018-11-14T13:29:23Z
dc.date.available2018-11-14T13:29:23Z
dc.date.issued2011
dc.identifier.citationNieto, A., Brea, V., Vilariño, D., & Osorio, R. (2011). Performance analysis of massively parallel embedded hardware architectures for retinal image processing. EURASIP Journal On Image And Video Processing, 2011(1). doi: 10.1186/1687-5281-2011-10
dc.identifier.issn1687-5176
dc.identifier.urihttp://hdl.handle.net/10347/17715
dc.description.abstractThis paper examines the implementation of a retinal vessel tree extraction technique on different hardware platforms and architectures. Retinal vessel tree extraction is a representative application of those found in the domain of medical image processing. The low signal-to-noise ratio of the images leads to a large amount of low-level tasks in order to meet the accuracy requirements. In some applications, this might compromise computing speed. This paper is focused on the assessment of the performance of a retinal vessel tree extraction method on different hardware platforms. In particular, the retinal vessel tree extraction method is mapped onto a massively parallel SIMD (MP-SIMD) chip, a massively parallel processor array (MPPA) and onto an field-programmable gate arrays (FPGA)
dc.description.sponsorshipThis work is funded by Xunta de Galicia under the projects 10PXIB206168PR and 10PXIB206037PR and the program Maria Barbeito
dc.language.isoeng
dc.publisherSpringer
dc.rights© Nieto et al; licensee Springer. 2011 This article is published under license to BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited
dc.rights.urihttps://creativecommons.org/licenses/by/2.0/
dc.subjectActive Contour
dc.subjectRetinal Image
dc.subjectExternal Memory
dc.subjectInitial Contour
dc.subjectProcessor Array
dc.titlePerformance analysis of massively parallel embedded hardware architectures for retinal image processing
dc.typejournal article
dc.identifier.doi10.1186/1687-5281-2011-10
dc.relation.publisherversionhttps://doi.org/10.1186/1687-5281-2011-10
dc.type.hasVersionVoR
dc.identifier.essn1687-5281
dc.rights.accessRightsopen access
dc.contributor.affiliationUniversidade de Santiago de Compostela. Centro de Investigación en Tecnoloxías da Información
dc.contributor.affiliationUniversidade de Santiago de Compostela. Departamento de Electrónica e Computación
dc.description.peerreviewedSI


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Mostrar o rexistro simple do ítem

© Nieto et al; licensee Springer. 2011 This article is published under license to BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited
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 © Nieto et al; licensee Springer. 2011 This article is published under license to BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited





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