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dc.contributor.author | Nieto Lareo, Alejandro Manuel |
dc.contributor.author | Brea Sánchez, Víctor Manuel |
dc.contributor.author | López Vilariño, David |
dc.contributor.author | Osorio, Roberto R. |
dc.date.accessioned | 2018-11-14T13:29:23Z |
dc.date.available | 2018-11-14T13:29:23Z |
dc.date.issued | 2011 |
dc.identifier.citation | Nieto, A., Brea, V., Vilariño, D., & Osorio, R. (2011). Performance analysis of massively parallel embedded hardware architectures for retinal image processing. EURASIP Journal On Image And Video Processing, 2011(1). doi: 10.1186/1687-5281-2011-10 |
dc.identifier.issn | 1687-5176 |
dc.identifier.uri | http://hdl.handle.net/10347/17715 |
dc.description.abstract | This paper examines the implementation of a retinal vessel tree extraction technique on different hardware platforms and architectures. Retinal vessel tree extraction is a representative application of those found in the domain of medical image processing. The low signal-to-noise ratio of the images leads to a large amount of low-level tasks in order to meet the accuracy requirements. In some applications, this might compromise computing speed. This paper is focused on the assessment of the performance of a retinal vessel tree extraction method on different hardware platforms. In particular, the retinal vessel tree extraction method is mapped onto a massively parallel SIMD (MP-SIMD) chip, a massively parallel processor array (MPPA) and onto an field-programmable gate arrays (FPGA) |
dc.description.sponsorship | This work is funded by Xunta de Galicia under the projects 10PXIB206168PR and 10PXIB206037PR and the program Maria Barbeito |
dc.language.iso | eng |
dc.publisher | Springer |
dc.rights | © Nieto et al; licensee Springer. 2011 This article is published under license to BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited |
dc.rights.uri | https://creativecommons.org/licenses/by/2.0/ |
dc.subject | Active Contour |
dc.subject | Retinal Image |
dc.subject | External Memory |
dc.subject | Initial Contour |
dc.subject | Processor Array |
dc.title | Performance analysis of massively parallel embedded hardware architectures for retinal image processing |
dc.type | journal article |
dc.identifier.doi | 10.1186/1687-5281-2011-10 |
dc.relation.publisherversion | https://doi.org/10.1186/1687-5281-2011-10 |
dc.type.hasVersion | VoR |
dc.identifier.essn | 1687-5281 |
dc.rights.accessRights | open access |
dc.contributor.affiliation | Universidade de Santiago de Compostela. Centro de Investigación en Tecnoloxías da Información |
dc.contributor.affiliation | Universidade de Santiago de Compostela. Departamento de Electrónica e Computación |
dc.description.peerreviewed | SI |
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© Nieto et al; licensee Springer. 2011 This article is published under license to BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited
© Nieto et al; licensee Springer. 2011 This article is published under license to BioMed Central Ltd. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/2.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited